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GATE Question Of The Day - Digital Electronics

 For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible





 Which of the following statements is true?

            (A)        Q goes to 1 at the CLK transition and stays at 1
            (B)        Q goes to 0 at the CLK transition and stays at 0
            (C)        Q goes to 1 at the CLK transition and goes to 0 when D goes to 1
            (D)        Q goes to 0 at the CLK transition and goes to 1 when D goes to 1

Pick up the correct options guys just a simple thing for my well wished friend(s)!

7 comments:

Vamshi said...

D

SouravMani said...

why my guys what happen to you??? i hope you all busy with week end's!

SouravMani said...

yes dude! you are right the correct answer is option ""D"".

peehu jain said...

I think the correct option is 'B'.

peehu jain said...

I think the correct option is 'B'.

Biren said...

I go for "B"

Anonymous said...

sairam says its b

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